Modern high speed electronic data processing systems often comprise a processor or CPU and a hierarchical memory system including a high capacity relatively low speed memory whose cycle time is much less than the cycle time of the processor and a relatively low capacity high speed memory, conventionally known as a cache, which has a memory cycle time comparable to the cycle time of the processor. Such cache memory systems are well known in the art for reducing effective memory access time at a more or less reasonable cost. When information is required by the CPU, it is read from the main memory, provided to the processor and written into the cache memory. If the same information is required subsequently by the processor, it may be read directly from the cache memory to avoid the time delay which would normally be encountered when reading the main memory.
However, if the cache memory is filled, the required information must be obtained from the main memory and the storage location in the cache memory must be identified for storing this new information. However, before the old location can be used for storing the new data, a determination must be made to see if the data currently in the cache has been modified by the program and if so, it must be stored back into the main memory in order that the main memory will properly reflect the current state of the data (if required). Most current cache architectures require such store back however it would obviously be advantageous to delete this store back function if the data in its modified form, will not again be needed by the program or if the data were never modified.
Another common feature present in most existing cache architectures is that they are essentially transparent to the system software. That is, the system software including compilers, operating systems etc. utilize memory fetch and store operations as though the cache did not exist. In such systems the hardware of the cache in essence interposes itself between the CPU and the main memory. In such system the existence of the cache greatly speed up effective memory access time however many of the benefits which could be derived from such a high speed storage are lost due to the architectures and conventions used.
An article entitled "The 801 Minicomputer," by George Radin, published in the ACM SIGPLAN Notices, Vol. 17, No. 4, April 1982, pages 39-47, is an overview of an experimental minicomputer which incorporates a hierarchical memory organization including separate cache memories for instructions and data including the teachings of the present invention.
U.S. Pat. No. 4,142,234 assigned to the same assignee as the present invention; an article entitled "Cache Memory with Prefetching Data Priority," by B. Bennett et al in the IBM Technical Disclosure Bulletin, Vol. 18, No. 12, May 1976; and U.S. Pat. No. 4,056,844 all generally disclose hierarchical memory organizations including cache memories wherein the cache memories are neither subdivided into separate data and instruction sections nor do they contain special control fields accessible to the program for controlling the operation of the memory system.
U.S. Pat. No. 4,161,024 and U.S. Pat. No. 4,195,342 both describe EDP systems which include direct CPU to cache interfaces as are generally known in the art.
U.S. Pat. No. 4,070,706 discloses a cache memory system in which the cache is divided into a data section and an address section (not a directory) but not into data and instruction sections.
U.S. Pat. No. 4,245,304 described a split cache system which divides the operation into two half cycles which enables the accessing of instructions from the cache or writing data into the cache during the same half cycle. This patent neither discloses nor suggests special control bits in the cache directory for controlling cache/main memory operations.
U.S. Pat. No. 4,075,686 describes a cache storage system which selectively bypasses the cache in accordance with the coding of a particular instruction bit in a memory access operation thereby shortening execution time for certain types of operations.
U.S. Pat. No. 4,142,234 discloses a cache system which eliminates particular interrogations of the cache directory to reduce the size of the spec.
U.S. Pat. No. 3,618,041 and an article entitled "Split Cache with Variable Interleave Boundary," by G. C. Driscoll et al in the IBM Technical Disclosure Bulletin, Vol, 22, No. 11, April 1980, page 5183, both broadly disclose the basic concept of splitting a cache subsystem into separate instruction and data sections and providing complex operating system support for the overlapped operation of the two separate caches.
U.S. Pat. No. 4,197,580 broadly discloses a single cache subsystem which utilizes a special validity bit and a "tag" which is used to control certain read-write operations. This bit is used to avoid unnecessary cache cycles rather than main memory cycles which latter result is the intent of the present invention.